Design and Implementation of a Low Power and Area Efficient Sequential Multiplier
Keywords:
Shift and add multiplier, Controller, Power consumption, Area, XilinxAbstract
A multiplier plays a major role in various digital systems. The area, speed and power consumption of any digital
system, which has a multiplier as its component, depend upon the hardware used for the multiplier. In this paper
we proposed a sequential multiplier which has a lower area requirement and lower power consumption in
comparison of the conventional sequential multiplier. We can use the proposed system where long battery life is
required and/or reduced hardware is required. The speed of the proposed multiplier is a little bit slower than the
conventional one. So we can use the proposed system where long battery life is required and speed is not the
major requirement.
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References
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