Design and Implementation of a Low Power and Area Efficient Sequential Multiplier

Authors

  • Mohit Kumar Department of Electronics & Communication Engineering Graphic Era University, Dehradun, India
  • Subhash Chandra Yadav Department of Electronics & Communication Engineering Graphic Era University, Dehradun, India

Keywords:

Shift and add multiplier, Controller, Power consumption, Area, Xilinx

Abstract

A multiplier plays a major role in various digital systems. The area, speed and power consumption of any digital
system, which has a multiplier as its component, depend upon the hardware used for the multiplier. In this paper
we proposed a sequential multiplier which has a lower area requirement and lower power consumption in
comparison of the conventional sequential multiplier. We can use the proposed system where long battery life is
required and/or reduced hardware is required. The speed of the proposed multiplier is a little bit slower than the
conventional one. So we can use the proposed system where long battery life is required and speed is not the
major requirement.

Downloads

Download data is not yet available.

References

Chandrakasan, A. P., Sheng, S., & Brodersen, R. W. (1992). Low-power CMOS digital design. IEICE

Transactions on Electronics, 75(4), 371-382.

Chen, O. C., Wang, S., & Wu, Y. W. (2003). Minimization of switching activities of partial products for

designing low-power multipliers. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 11(3),

-433.

Jayaprakash, M., Mohamed, M. P., & Shanmugam, A. (2011). Design and Analysis of Low Power and Area

Efficient Multiplier. International Journal of Electrical, Electronics and Mechanical Controls ISSN (Online),

-7501.

Kulkarni, P. D., Deshpande, S. P., & Udupi, G. R. (2013) low Power Add and Shift Multiplier Design BZFAD

Architecture. International Journal of Computer and Electronics Research, 2(2),94-107.

Marimuthu, C. N., Thangaraj, P., & Ramesan, A. (2010). Low power shift and add multiplier design. arXiv

preprint arXiv:1006.1179.

Moshnyaga, V. G., & Tamaru, K. (1995, April). A comparative study of switching activity reduction techniques

for design of low-power multipliers. InCircuits and Systems, 1995. ISCAS'95., 1995 IEEE International

Symposium on (Vol. 3, pp. 1560-1563). IEEE.

Shen, N. Y., & Chen, O. C. (2002). Low-power multipliers by minimizing switching activities of partial

products. In Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on (Vol. 4, pp. IV-93).

IEEE

Downloads

Published

2023-02-28

How to Cite

Kumar, M., & Yadav, S. C. (2023). Design and Implementation of a Low Power and Area Efficient Sequential Multiplier. Journal of Graphic Era University, 4(1), 41–48. Retrieved from https://riverpublishersjournal.com/index.php/JGEU/article/view/127

Issue

Section

Articles